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IRQ based tag polling

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This commit is contained in:
uvos
2022-03-10 22:25:35 +01:00
parent b01caeda28
commit 97aa264b54
5 changed files with 448 additions and 112 deletions
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263
mfrc522.cpp
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@ -1,6 +1,7 @@
#include "mfrc522.h"
Serial *Mfrc522::serial = nullptr;
uint8_t Mfrc522::reponseBuffer[Mfrc522::reponseBufferLen];
uint8_t Mfrc522::read(uint8_t addr)
{
@ -58,25 +59,26 @@ void Mfrc522::updateBit(uint8_t addr, uint8_t bit, bool value)
void (*_tagEnterdCb)(Mfrc522*, void*);
void* _userData;
Mfrc522::Mfrc522(SpiMaster* spi, ShiftReg<NFC_PORTS>* csReg, uint8_t csPin,
void (*tagEnterdCb)(Mfrc522*, void*), void* userData):
_csReg(csReg), _spi(spi), _csPin(csPin), _tagEnterdCb(tagEnterdCb), _userData(userData)
Mfrc522::Mfrc522(SpiMaster* spi, ShiftReg<NFC_PORTS>* csReg, uint8_t csPin):
_csReg(csReg), _spi(spi), _csPin(csPin)
{
write(CommandReg, SOFTRESET);
_delay_ms(100);
write(TModeReg, 0x80);
write(TPrescalerReg, 0xA9);
write(TReloadRegH, 0x03);
write(TReloadRegL, 0xE8);
write(TReloadRegH, 0x0B);
write(TReloadRegL, 0xB8);
write(ModWidthReg, 0x26);
write(RFCfgReg, 0b111 << 4); //set gain to 48dB
write(TxAutoReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
updateBit(RxModeReg, 3, true);
write(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
//write(DivIEnReg, 0b10010000); // enable MfinActIrq as push-pull
//write(ComIEnReg, 0b00100000); // enable Rx irq
write(ComIrqReg, 0b01111111);
write(ComIEnReg, 0); // invert irq pin (high is active)
write(DivIEnReg, 1 << 7); // enable MfinActIrq as push-pull
setRf(true);
}
@ -112,18 +114,12 @@ uint8_t Mfrc522::calculateCrc(uint8_t *data, uint8_t length, uint16_t *result)
return 0;
}
uint8_t Mfrc522::commuicateWithTag(uint8_t command, uint8_t waitIrq,
uint8_t *sendData, uint8_t sendLen,
uint8_t *recvData, uint8_t *recvLen,
uint8_t validBits, uint8_t rxAlign,
uint8_t *rxValidBits)
void Mfrc522::setupTransceive(uint8_t *sendData, uint8_t sendLen, uint8_t validBits, uint8_t rxAlign)
{
write(CommandReg, IDLE);
write(ComIrqReg, 0b01111111); // clear irqs
write(FIFOLevelReg, 1 << 7); // Flush fifo Buffer;
write(FIFODataReg, sendData, sendLen); // Fill fifo
write(BitFramingReg, (rxAlign << 4) + validBits);
write(CommandReg, command); // Execute the command
write(CommandReg, TRANSCEIVE); // Execute the command
if(serial)
{
@ -140,14 +136,82 @@ uint8_t Mfrc522::commuicateWithTag(uint8_t command, uint8_t waitIrq,
serial->write((int)read(BitFramingReg));
serial->putChar('\n');
}
updateBit(BitFramingReg, 7, true);
}
uint8_t Mfrc522::transceiveAsync(void (*transceiveCb)(uint8_t, Mfrc522*, uint8_t*, uint8_t, void*), void* userData,
uint8_t *sendData, uint8_t sendLen, uint8_t validBits, uint8_t rxAlign)
{
if(mode != MODE_IDLE)
return BUSY;
mode = MODE_TRANSCEIVE;
if (command == TRANSCEIVE)
updateBit(BitFramingReg, 7, true);
_transceiveCb = transceiveCb;
_transceiveUserData = userData;
write(CommandReg, IDLE);
write(ComIrqReg, 0b01111111); // clear irqs
write(ComIEnReg, (1 << 5) | (1 << 0));
setupTransceive(sendData, sendLen, validBits, rxAlign);
return 0;
}
void Mfrc522::transceiveAsyncFinish(uint8_t irq)
{
write(ComIEnReg, 0); // disable irqs
if(!_transceiveCb)
{
mode = MODE_IDLE;
updateBit(FIFOLevelReg, 7, true);
return;
}
uint8_t errorRegValue = read(ErrorReg);
if (errorRegValue & 0b00010011) // BufferOvfl ParityErr ProtocolErr
{
mode = MODE_IDLE;
_transceiveCb(ERR, this, nullptr, 0, _transceiveUserData);
return;
}
if(irq & 1)
{
mode = MODE_IDLE;
_transceiveCb(TIMEOUT, this, nullptr, 0, _transceiveUserData);
return;
}
uint8_t fifoBites = read(FIFOLevelReg);
if(fifoBites > reponseBufferLen)
_transceiveCb(LEN, this, nullptr, 0, _transceiveUserData);
read(FIFODataReg, reponseBuffer, fifoBites);
mode = MODE_IDLE;
if(errorRegValue & 0x08)
_transceiveCb(COLLISION, this, reponseBuffer, fifoBites, _transceiveUserData);
else
_transceiveCb(0, this, reponseBuffer, fifoBites, _transceiveUserData);
}
uint8_t Mfrc522::transceive(uint8_t *sendData, uint8_t sendLen,
uint8_t *recvData, uint8_t *recvLen,
uint8_t validBits, uint8_t rxAlign,
uint8_t *rxValidBits)
{
write(CommandReg, IDLE);
write(ComIrqReg, 0b01111111); // clear irqs
setupTransceive(sendData, sendLen, validBits, rxAlign);
uint16_t i = 2000;
uint8_t irq = read(ComIrqReg);
while(irq & waitIrq)
while(!(irq & 0x30)) // RxIRq and IdleIRq
{
irq = read(ComIrqReg);
if(irq & 0x01 || --i == 0)
@ -200,13 +264,6 @@ uint8_t Mfrc522::commuicateWithTag(uint8_t command, uint8_t waitIrq,
return 0;
}
uint8_t Mfrc522::transceive(uint8_t *sendData, uint8_t sendLen, uint8_t *recvData, uint8_t *recvLen,
uint8_t validBits, uint8_t rxAlign, uint8_t *rxValidBits)
{
uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
return commuicateWithTag(TRANSCEIVE, waitIRq, sendData, sendLen, recvData,
recvLen, validBits, rxAlign, rxValidBits);
}
uint8_t Mfrc522::wakeupTag(uint8_t* bufferATQA, uint8_t *bufferLen)
{
@ -234,14 +291,13 @@ uint8_t Mfrc522::selectTag(Uid *uid)
uint8_t index;
uint8_t uidIndex; // The first index in uid->uidByte[] that is used in the current Cascade Level.
int8_t currentLevelKnownBits; // The number of known UID bits in the current Cascade Level.
uint8_t buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 uint8_t standard frame + 2 uint8_ts CRC_A
uint8_t bufferUsed; // The number of uint8_ts used in the buffer, ie the number of uint8_ts to transfer to the FIFO
uint8_t txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted uint8_t.
uint8_t *responseBuffer;
uint8_t *responseBufferPtr;
uint8_t responseLength;
if(serial)
serial->write_p(PSTR("Select\n"));
serial->write_p(PSTR("Select\n"));
// Description of buffer structure:
// Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3
@ -277,17 +333,17 @@ uint8_t Mfrc522::selectTag(Uid *uid)
switch(cascadeLevel)
{
case 0:
buffer[0] = PICC_CMD_SEL_CL1;
reponseBuffer[0] = PICC_CMD_SEL_CL1;
uidIndex = 0;
break;
case 1:
buffer[0] = PICC_CMD_SEL_CL2;
reponseBuffer[0] = PICC_CMD_SEL_CL2;
uidIndex = 3;
break;
case 2:
buffer[0] = PICC_CMD_SEL_CL3;
reponseBuffer[0] = PICC_CMD_SEL_CL3;
uidIndex = 6;
break;
@ -309,7 +365,7 @@ uint8_t Mfrc522::selectTag(Uid *uid)
if (bytesToCopy > maxBytes)
bytesToCopy = maxBytes;
for (count = 0; count < bytesToCopy; count++)
buffer[index++] = uid->uidByte[uidIndex + count];
reponseBuffer[index++] = uid->uidByte[uidIndex + count];
}
// Repeat anti collision loop until we can transmit all UID bits + BCC and receive a SAK - max 32 iterations.
@ -319,11 +375,11 @@ uint8_t Mfrc522::selectTag(Uid *uid)
// Find out how many bits and bytes to send and receive.
if (currentLevelKnownBits >= 32) // All UID bits in this Cascade Level are known. This is a SELECT.
{
buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes
reponseBuffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes
// Calculate BCC - Block Check Character
buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5];
reponseBuffer[6] = reponseBuffer[2] ^ reponseBuffer[3] ^ reponseBuffer[4] ^ reponseBuffer[5];
// Calculate CRC_A
result = calculateCrc(buffer, 7, reinterpret_cast<uint16_t*>(&buffer[7]));
result = calculateCrc(reponseBuffer, 7, reinterpret_cast<uint16_t*>(&reponseBuffer[7]));
if (result != 0)
{
if(serial)
@ -333,7 +389,7 @@ uint8_t Mfrc522::selectTag(Uid *uid)
txLastBits = 0; // 0 => All 8 bits are valid.
bufferUsed = 9;
// Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx)
responseBuffer = &buffer[6];
responseBufferPtr = &reponseBuffer[6];
responseLength = 3;
}
else // This is an ANTICOLLISION.
@ -341,11 +397,11 @@ uint8_t Mfrc522::selectTag(Uid *uid)
txLastBits = currentLevelKnownBits % 8;
count = currentLevelKnownBits / 8; // Number of whole bytes in the UID part.
index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs
buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits
reponseBuffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits
bufferUsed = index + (txLastBits ? 1 : 0);
// Store response in the unused part of buffer
responseBuffer = &buffer[index];
responseLength = sizeof(buffer) - index;
responseBufferPtr = &reponseBuffer[index];
responseLength = sizeof(reponseBuffer) - index;
}
// Set bit adjustments
@ -365,7 +421,7 @@ uint8_t Mfrc522::selectTag(Uid *uid)
}
// Transmit the buffer and receive the response.
result = transceive(buffer, bufferUsed, responseBuffer, &responseLength, txLastBits, rxAlign, &txLastBits);
result = transceive(reponseBuffer, bufferUsed, responseBufferPtr, &responseLength, txLastBits, rxAlign, &txLastBits);
if (result == COLLISION) // More than one PICC in the field => collision.
{
result = read(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0]
@ -390,7 +446,7 @@ uint8_t Mfrc522::selectTag(Uid *uid)
count = currentLevelKnownBits % 8; // The bit to modify
checkBit = (currentLevelKnownBits - 1) % 8;
index = 1 + (currentLevelKnownBits / 8) + (count ? 1 : 0); // First byte is index 0.
buffer[index] |= (1 << checkBit);
reponseBuffer[index] |= (1 << checkBit);
}
else if (result != 0)
{
@ -410,11 +466,11 @@ uint8_t Mfrc522::selectTag(Uid *uid)
// We do not check the CBB - it was constructed by us above.
// Copy the found UID bytes from buffer[] to uid->uidByte[]
index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[]
bytesToCopy = (buffer[2] == PICC_CMD_CT) ? 3 : 4;
index = (reponseBuffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[]
bytesToCopy = (reponseBuffer[2] == PICC_CMD_CT) ? 3 : 4;
for (count = 0; count < bytesToCopy; count++)
{
uid->uidByte[uidIndex + count] = buffer[index++];
uid->uidByte[uidIndex + count] = reponseBuffer[index++];
}
// Check response SAK (Select Acknowledge)
@ -431,19 +487,19 @@ uint8_t Mfrc522::selectTag(Uid *uid)
return ERR;
}
// Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore.
result = calculateCrc(responseBuffer, 1, reinterpret_cast<uint16_t*>(&buffer[2]));
result = calculateCrc(responseBufferPtr, 1, reinterpret_cast<uint16_t*>(&reponseBuffer[2]));
if (result != 0)
return result;
if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2]))
if ((reponseBuffer[2] != responseBufferPtr[1]) || (reponseBuffer[3] != responseBufferPtr[2]))
return CRC;
if (responseBuffer[0] & 0x04) // Cascade bit set - UID not complete yes
if (responseBufferPtr[0] & 0x04) // Cascade bit set - UID not complete yes
{
cascadeLevel++;
}
else
{
uidComplete = true;
uid->sak = responseBuffer[0];
uid->sak = responseBufferPtr[0];
}
} // End of while ( ! uidComplete)
@ -453,9 +509,53 @@ uint8_t Mfrc522::selectTag(Uid *uid)
return 0;
}
uint8_t Mfrc522::getUid(Uid *uid)
{
uint8_t bufferOut[2];
uint8_t reponseBuffer[5];
bufferOut[0] = PICC_CMD_SEL_CL1;
bufferOut[1] = 2 << 4;
uint8_t rxLen = sizeof(reponseBuffer);
uint8_t ret = transceive(bufferOut, 2, reponseBuffer, &rxLen);
if(ret != 0)
return ret;
if(rxLen != 5)
return ERR;
uid->size = 4;
for(uint8_t i = 0; i < uid->size; ++i)
{
uid->uidByte[i] = reponseBuffer[i];
}
return 0;
}
void Mfrc522::irq()
{
if(mode == MODE_TRANSCEIVE)
{
uint8_t irqs = read(ComIrqReg);
if(irqs)
{
if(serial)
{
serial->write("IRQS: ");
serial->write((int)irqs);
serial->putChar('\n');
}
write(ComIrqReg, 0b01111111); // clear irqs
transceiveAsyncFinish(irqs);
}
}
else if(serial)
serial->write("IRQ wrong mode\n");
}
void Mfrc522::setRf(bool on)
@ -469,9 +569,8 @@ void Mfrc522::setRf(bool on)
bool Mfrc522::cardPresent()
{
uint8_t bufferATQA[2];
uint8_t bufferLen = sizeof(bufferATQA);
uint8_t ret = wakeupTag(bufferATQA, &bufferLen);
uint8_t bufferLen = sizeof(reponseBuffer);
uint8_t ret = wakeupTag(reponseBuffer, &bufferLen);
return ret == 0 || ret == COLLISION;
}
@ -480,6 +579,12 @@ bool Mfrc522::probe(SpiMaster* spi, ShiftReg<NFC_PORTS>* csReg, uint8_t csPin)
csReg->setBit(csPin, false);
spi->readWrite((VersionReg << 1) | (1 << 7));
uint8_t version = spi->readWrite();
if(serial)
{
serial->write_p(PSTR("Got version register: "));
serial->write((int)version);
serial->putChar('\n');
}
csReg->setBit(csPin, true);
return version == 0x91 || version == 0x92;
}
@ -487,7 +592,6 @@ bool Mfrc522::probe(SpiMaster* spi, ShiftReg<NFC_PORTS>* csReg, uint8_t csPin)
bool Mfrc522::testFifo()
{
uint8_t buffer[8] = {42, 43, 44, 45, 46, 47, 48, 49};
uint8_t buffer2[8] = {};
write(FIFOLevelReg, 1 << 7); // Flush fifo Buffer;
write(FIFODataReg, buffer, sizeof(buffer)); // Fill fifo
@ -495,15 +599,58 @@ bool Mfrc522::testFifo()
serial->write_p(PSTR("Fifo buffer contains: "));
uint8_t len = read(FIFOLevelReg);
read(FIFODataReg, buffer2, len);
read(FIFODataReg, reponseBuffer, len);
bool ret = true;
for(uint8_t i = 0; i < len; ++i)
{
if(buffer[i] != buffer2[i])
if(buffer[i] != reponseBuffer[i])
ret = false;
serial->write((int)buffer2[i]);
serial->putChar(' ');
if(serial)
{
serial->write((int)reponseBuffer[i]);
serial->putChar(' ');
}
}
serial->putChar('\n');
if(serial)
serial->putChar('\n');
return ret;
}
bool Mfrc522::detectAsync(void (*tagEnterdCb)(Mfrc522*, void*), void* userData)
{
if(irqDetect)
return false;
_tagEnterdCb = tagEnterdCb;
_userData = userData;
irqDetect = true;
updateBit(CollReg, 7, false);
uint8_t data = PICC_CMD_WUPA;
if(transceiveAsync(&detectAsyncCb, nullptr, &data, 1, 7) != 0)
{
irqDetect = false;
return false;
}
return true;
}
void Mfrc522::stopAsync()
{
write(CommandReg, IDLE);
write(FIFOLevelReg, 1 << 7);
mode = MODE_IDLE;
irqDetect = false;
}
void Mfrc522::detectAsyncCb(uint8_t ret, Mfrc522* reader, uint8_t* response, uint8_t responseLen, void* userData)
{
if((ret == 0 || ret == COLLISION) && reader->_tagEnterdCb)
{
reader->stopAsync();
reader->_tagEnterdCb(reader, reader->_userData);
}
else
{
reader->irqDetect = false;
reader->detectAsync(reader->_tagEnterdCb, reader->_userData);
}
}