510 lines
14 KiB
C++
510 lines
14 KiB
C++
#include "mfrc522.h"
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uint8_t Mfrc522::read(uint8_t addr)
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{
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_csReg->setBit(_csPin, false);
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_spi->readWrite((addr << 1) | (1 << 7));
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uint8_t res = _spi->readWrite();
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_csReg->setBit(_csPin, true);
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return res;
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}
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void Mfrc522::read(uint8_t addr, uint8_t* data, uint8_t datalen, uint8_t rxAlign)
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{
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_csReg->setBit(_csPin, false);
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const uint8_t addrS = addr << 1 | (1 << 7);
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_spi->readWrite(addrS);
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for(uint8_t i = 0; i < datalen; ++i)
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{
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if(i == 0 && rxAlign)
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{
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uint8_t mask = 0;
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for (uint8_t j = rxAlign; j <= 7; ++j)
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mask |= (1 << j);
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uint8_t value = _spi->readWrite(addrS);
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data[0] = (data[0] & ~mask) | (value & mask);
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}
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else
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{
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data[i] = _spi->readWrite(addrS);
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}
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}
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_csReg->setBit(_csPin, true);
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}
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void Mfrc522::write(uint8_t addr, uint8_t data)
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{
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_csReg->setBit(_csPin, false);
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_spi->readWrite(addr << 1);
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_spi->readWrite(data);
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_csReg->setBit(_csPin, true);
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}
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void Mfrc522::write(uint8_t addr, uint8_t* data, uint8_t datalen)
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{
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_csReg->setBit(_csPin, false);
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_spi->readWrite(addr << 1);
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_spi->readWrite(datalen, nullptr, data);
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_csReg->setBit(_csPin, true);
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}
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void Mfrc522::updateBit(uint8_t addr, uint8_t bit, bool value)
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{
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uint8_t old = read(addr);
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write(addr, value ? old | (1 << bit) : old & ~(1 << bit));
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}
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void (*_tagEnterdCb)(Mfrc522*, void*);
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void* _userData;
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Mfrc522::Mfrc522(SpiMaster* spi, ShiftReg<NFC_PORTS>* csReg, uint8_t csPin,
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void (*tagEnterdCb)(Mfrc522*, void*), void* userData):
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_csReg(csReg), _spi(spi), _csPin(csPin), _tagEnterdCb(tagEnterdCb), _userData(userData)
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{
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write(CommandReg, SOFTRESET);
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_delay_ms(100);
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write(TModeReg, 0x80);
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write(TPrescalerReg, 0xA9);
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write(TReloadRegH, 0x03);
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write(TReloadRegL, 0xE8);
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write(ModWidthReg, 0x26);
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write(RFCfgReg, 0b111 << 4); //set gain to 48dB
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write(TxAutoReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
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write(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
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//write(DivIEnReg, 0b10010000); // enable MfinActIrq as push-pull
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//write(ComIEnReg, 0b00100000); // enable Rx irq
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setRf(true);
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}
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uint8_t Mfrc522::calculateCrc(uint8_t *data, uint8_t length, uint16_t *result)
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{
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write(CommandReg, IDLE); // Stop any active command.
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write(DivIrqReg, 0x04); // Clear the CRCIRq interrupt request bit
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updateBit(FIFOLevelReg, 7, true); // FlushBuffer = 1, FIFO initialization
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write(FIFODataReg, data, length); // Write data to the FIFO
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write(CommandReg, CALCCRC); // Start the calculation
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// Wait for the CRC calculation to complete.
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uint16_t i = 5000;
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while(!(read(DivIrqReg) & 0x04) && i != 0)
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--i;
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if(i == 0)
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return ERR;
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write(CommandReg, IDLE);
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if(serial)
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{
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serial->write_p(PSTR("Calculated CRC "));
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serial->write((int)read(CRCResultRegL));
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serial->putChar(' ');
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serial->write((int)read(CRCResultRegH));
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serial->putChar('\n');
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}
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*result = read(CRCResultRegL);
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*result |= read(CRCResultRegH) << 8;
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return 0;
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}
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uint8_t Mfrc522::commuicateWithTag(uint8_t command, uint8_t waitIrq,
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uint8_t *sendData, uint8_t sendLen,
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uint8_t *recvData, uint8_t *recvLen,
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uint8_t validBits, uint8_t rxAlign,
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uint8_t *rxValidBits)
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{
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write(CommandReg, IDLE);
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write(ComIrqReg, 0b01111111); // clear irqs
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write(FIFOLevelReg, 1 << 7); // Flush fifo Buffer;
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write(FIFODataReg, sendData, sendLen); // Fill fifo
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write(BitFramingReg, (rxAlign << 4) + validBits);
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write(CommandReg, command); // Execute the command
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if(serial)
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{
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serial->write_p(PSTR("Communicate params: CommandReg: "));
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serial->write((int)read(CommandReg));
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serial->putChar(' ');
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serial->write_p(PSTR("FIFO: "));
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for(uint8_t i = 0; i < sendLen; ++i)
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{
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serial->write((int)sendData[i]);
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serial->putChar(' ');
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}
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serial->write_p(PSTR("BitFramingReg: "));
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serial->write((int)read(BitFramingReg));
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serial->putChar('\n');
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}
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if (command == TRANSCEIVE)
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updateBit(BitFramingReg, 7, true);
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uint16_t i = 2000;
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uint8_t irq = read(ComIrqReg);
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while(irq & waitIrq)
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{
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irq = read(ComIrqReg);
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if(irq & 0x01 || --i == 0)
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{
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if(serial)
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serial->write_p(PSTR("timeout\n"));
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return TIMEOUT;
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}
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}
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uint8_t errorRegValue = read(ErrorReg);
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if (errorRegValue & 0b00010011) // BufferOvfl ParityErr ProtocolErr
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{
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if(serial)
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serial->write_p(PSTR("BufferOvfl ParityErr ProtocolErr\n"));
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return ERR;
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}
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if (recvData && recvLen)
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{
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uint8_t fifoBites = read(FIFOLevelReg);
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if(fifoBites > *recvLen)
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return LEN;
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*recvLen = fifoBites;
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read(FIFODataReg, recvData, fifoBites, rxAlign);
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if(rxValidBits)
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*rxValidBits = read(ControlReg) & 0x07;
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if(serial)
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{
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serial->write_p(PSTR("fifo has "));
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serial->write((int)fifoBites);
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serial->write_p(PSTR(" bytes: "));
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for(uint8_t i = 0; i < fifoBites; ++i)
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{
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serial->write((int)recvData[i]);
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serial->putChar(' ');
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}
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serial->putChar('\n');
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}
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}
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if(errorRegValue & 0x08)
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{
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if(serial)
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serial->write_p(PSTR("collision err\n"));
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return COLLISION;
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}
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return 0;
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}
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uint8_t Mfrc522::transceive(uint8_t *sendData, uint8_t sendLen, uint8_t *recvData, uint8_t *recvLen,
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uint8_t validBits, uint8_t rxAlign, uint8_t *rxValidBits)
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{
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uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
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return commuicateWithTag(TRANSCEIVE, waitIRq, sendData, sendLen, recvData,
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recvLen, validBits, rxAlign, rxValidBits);
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}
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uint8_t Mfrc522::wakeupTag(uint8_t* bufferATQA, uint8_t *bufferLen)
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{
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if(*bufferLen < 2)
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return ERR;
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updateBit(CollReg, 7, false);
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uint8_t data = PICC_CMD_WUPA;
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uint8_t ret = transceive(&data, 1, bufferATQA, bufferLen, 7);
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if(*bufferLen != 2)
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return ERR;
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return ret;
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}
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uint8_t Mfrc522::selectTag(Uid *uid)
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{
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bool uidComplete;
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bool selectDone;
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uint8_t cascadeLevel = 0;
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uint8_t result;
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uint8_t count;
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uint8_t checkBit;
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uint8_t index;
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uint8_t uidIndex; // The first index in uid->uidByte[] that is used in the current Cascade Level.
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int8_t currentLevelKnownBits; // The number of known UID bits in the current Cascade Level.
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uint8_t buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 uint8_t standard frame + 2 uint8_ts CRC_A
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uint8_t bufferUsed; // The number of uint8_ts used in the buffer, ie the number of uint8_ts to transfer to the FIFO
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uint8_t txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted uint8_t.
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uint8_t *responseBuffer;
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uint8_t responseLength;
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if(serial)
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serial->write_p(PSTR("Select\n"));
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// Description of buffer structure:
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// Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3
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// Byte 1: NVB Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits.
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// Byte 2: UID-data or CT See explanation below. CT means Cascade Tag.
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// Byte 3: UID-data
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// Byte 4: UID-data
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// Byte 5: UID-data
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// Byte 6: BCC Block Check Character - XOR of bytes 2-5
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// Byte 7: CRC_A
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// Byte 8: CRC_A
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// The BCC and CRC_A is only transmitted if we know all the UID bits of the current Cascade Level.
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//
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// Description of bytes 2-5: (Section 6.5.4 of the ISO/IEC 14443-3 draft: UID contents and cascade levels)
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// UID size Cascade level Byte2 Byte3 Byte4 Byte5
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// ======== ============= ===== ===== ===== =====
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// 4 bytes 1 uid0 uid1 uid2 uid3
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// 7 bytes 1 CT uid0 uid1 uid2
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// 2 uid3 uid4 uid5 uid6
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// 10 bytes 1 CT uid0 uid1 uid2
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// 2 CT uid3 uid4 uid5
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// 3 uid6 uid7 uid8 uid9
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// Prepare MFRC522
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updateBit(CollReg, 7, false); // ValuesAfterColl=1 => Bits received after collision are cleared.
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// Repeat Cascade Level loop until we have a complete UID.
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uidComplete = false;
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currentLevelKnownBits = 0;
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while(!uidComplete)
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{
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// Set the Cascade Level in the SEL byte, find out if we need to use the Cascade Tag in byte 2.
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switch(cascadeLevel)
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{
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case 0:
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buffer[0] = PICC_CMD_SEL_CL1;
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uidIndex = 0;
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break;
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case 1:
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buffer[0] = PICC_CMD_SEL_CL2;
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uidIndex = 3;
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break;
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case 2:
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buffer[0] = PICC_CMD_SEL_CL3;
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uidIndex = 6;
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break;
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default:
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if(serial)
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serial->write_p(PSTR("err cascadeLevel\n"));
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return ERR;
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break;
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}
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// Copy the known bits from uid->uidByte[] to buffer[]
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index = 2; // destination index in buffer[]
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// The number of bytes needed to represent the known bits for this level.
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uint8_t bytesToCopy = currentLevelKnownBits / 8 + (currentLevelKnownBits % 8 ? 1 : 0);
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if(bytesToCopy)
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{
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// Max 4 bytes in each Cascade Level. Only 3 left if we use the Cascade Tag
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uint8_t maxBytes = 4;
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if (bytesToCopy > maxBytes)
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bytesToCopy = maxBytes;
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for (count = 0; count < bytesToCopy; count++)
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buffer[index++] = uid->uidByte[uidIndex + count];
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}
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// Repeat anti collision loop until we can transmit all UID bits + BCC and receive a SAK - max 32 iterations.
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selectDone = false;
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while (!selectDone)
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{
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// Find out how many bits and bytes to send and receive.
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if (currentLevelKnownBits >= 32) // All UID bits in this Cascade Level are known. This is a SELECT.
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{
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buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes
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// Calculate BCC - Block Check Character
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buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5];
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// Calculate CRC_A
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result = calculateCrc(buffer, 7, reinterpret_cast<uint16_t*>(&buffer[7]));
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if (result != 0)
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{
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if(serial)
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serial->write_p(PSTR("err calculateCrc\n"));
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return result;
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}
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txLastBits = 0; // 0 => All 8 bits are valid.
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bufferUsed = 9;
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// Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx)
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responseBuffer = &buffer[6];
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responseLength = 3;
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}
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else // This is an ANTICOLLISION.
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{
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txLastBits = currentLevelKnownBits % 8;
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count = currentLevelKnownBits / 8; // Number of whole bytes in the UID part.
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index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs
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buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits
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bufferUsed = index + (txLastBits ? 1 : 0);
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// Store response in the unused part of buffer
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responseBuffer = &buffer[index];
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responseLength = sizeof(buffer) - index;
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}
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// Set bit adjustments
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uint8_t rxAlign = txLastBits;
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// RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
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write(BitFramingReg, (rxAlign << 4) + txLastBits);
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if(serial)
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{
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serial->write_p(PSTR("entering transceive "));
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serial->write((int)responseLength);
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serial->putChar(' ');
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serial->write((int)txLastBits);
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serial->putChar(' ');
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serial->write((int)currentLevelKnownBits);
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serial->putChar('\n');
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}
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// Transmit the buffer and receive the response.
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result = transceive(buffer, bufferUsed, responseBuffer, &responseLength, txLastBits, rxAlign, &txLastBits);
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if (result == COLLISION) // More than one PICC in the field => collision.
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{
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result = read(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0]
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if (result & 0x20)
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{
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if(serial)
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serial->write_p(PSTR("err collision\n"));
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return COLLISION; // Without a valid collision position we cannot continue
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}
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uint8_t collisionPos = result & 0x1F; // Values 0-31, 0 means bit 32.
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if (collisionPos == 0) {
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collisionPos = 32;
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}
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if (collisionPos <= currentLevelKnownBits) // No progress - should not happen
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{
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if(serial)
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serial->write_p(PSTR("err No progress\n"));
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return ERR;
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}
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// Choose the PICC with the bit set.
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currentLevelKnownBits = collisionPos;
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count = currentLevelKnownBits % 8; // The bit to modify
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checkBit = (currentLevelKnownBits - 1) % 8;
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index = 1 + (currentLevelKnownBits / 8) + (count ? 1 : 0); // First byte is index 0.
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buffer[index] |= (1 << checkBit);
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}
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else if (result != 0)
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{
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if(serial)
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serial->write_p(PSTR("err transceive\n"));
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return result;
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}
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else
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{
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if (currentLevelKnownBits >= 32) // This was a SELECT.
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selectDone = true;
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else // This was an ANTICOLLISION. Run loop again to do the SELECT.
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currentLevelKnownBits = 32;
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}
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}
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// We do not check the CBB - it was constructed by us above.
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// Copy the found UID bytes from buffer[] to uid->uidByte[]
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index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[]
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bytesToCopy = (buffer[2] == PICC_CMD_CT) ? 3 : 4;
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for (count = 0; count < bytesToCopy; count++)
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{
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uid->uidByte[uidIndex + count] = buffer[index++];
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}
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// Check response SAK (Select Acknowledge)
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if (responseLength != 3 || txLastBits != 0) // SAK must be exactly 24 bits (1 byte + CRC_A).
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{
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if(serial)
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{
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serial->write_p(PSTR("err SAK "));
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serial->write((int)responseLength);
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serial->putChar(' ');
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serial->write((int)txLastBits);
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serial->putChar('\n');
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}
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return ERR;
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}
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// Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore.
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result = calculateCrc(responseBuffer, 1, reinterpret_cast<uint16_t*>(&buffer[2]));
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if (result != 0)
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return result;
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if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2]))
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return CRC;
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if (responseBuffer[0] & 0x04) // Cascade bit set - UID not complete yes
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{
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cascadeLevel++;
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}
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else
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{
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uidComplete = true;
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uid->sak = responseBuffer[0];
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}
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} // End of while ( ! uidComplete)
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// Set correct uid->size
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uid->size = 3 * (cascadeLevel+1) + 1;
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return 0;
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}
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void Mfrc522::irq()
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{
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}
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void Mfrc522::setRf(bool on)
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{
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uint8_t value = read(TxControlReg);
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if(on && (value & 0x03) != 0x03)
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write(TxControlReg, value | 0x03);
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else if(!on && (value & 0x03) != 0x00)
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write(TxControlReg, value & ~0x03);
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}
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bool Mfrc522::cardPresent()
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{
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uint8_t bufferATQA[2];
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uint8_t bufferLen = sizeof(bufferATQA);
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uint8_t ret = wakeupTag(bufferATQA, &bufferLen);
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return ret == 0 || ret == COLLISION;
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}
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bool Mfrc522::probe(SpiMaster* spi, ShiftReg<NFC_PORTS>* csReg, uint8_t csPin)
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{
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csReg->setBit(csPin, false);
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spi->readWrite((VersionReg << 1) | (1 << 7));
|
|
uint8_t version = spi->readWrite();
|
|
csReg->setBit(csPin, true);
|
|
return version == 0x91 || version == 0x92;
|
|
}
|
|
|
|
bool Mfrc522::testFifo()
|
|
{
|
|
uint8_t buffer[8] = {42, 43, 44, 45, 46, 47, 48, 49};
|
|
uint8_t buffer2[8] = {};
|
|
write(FIFOLevelReg, 1 << 7); // Flush fifo Buffer;
|
|
write(FIFODataReg, buffer, sizeof(buffer)); // Fill fifo
|
|
|
|
if(serial)
|
|
serial->write_p(PSTR("Fifo buffer contains: "));
|
|
|
|
uint8_t len = read(FIFOLevelReg);
|
|
read(FIFODataReg, buffer2, len);
|
|
bool ret = true;
|
|
for(uint8_t i = 0; i < len; ++i)
|
|
{
|
|
if(buffer[i] != buffer2[i])
|
|
ret = false;
|
|
serial->write((int)buffer2[i]);
|
|
serial->putChar(' ');
|
|
}
|
|
serial->putChar('\n');
|
|
return ret;
|
|
}
|