ModelTrain/TrainDecoder
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make inital state consistant, dehardcode address

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This commit is contained in:
uvos 2022-01-21 23:21:28 +01:00
parent cc9dd6eb19
commit 783fc72004
1 changed files with 5 additions and 8 deletions
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13
main.cpp
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@ -50,7 +50,7 @@ static void setTurnout1(bool in)
writePin(&PORTB, T1_B, false); writePin(&PORTB, T1_B, false);
} }
Decoder decoder(&PINB, PB2, &TCNT1, &handler); Decoder decoder(&PINB, PB2, &TCNT1, &handler, nullptr, 0x02);
ISR(TIMER1_OVF_vect) ISR(TIMER1_OVF_vect)
{ {
@ -66,14 +66,11 @@ int main()
{ {
DDRB = (1 << PB0) | (1 << PB1) | (1 << PB3) | (1 << PB4); DDRB = (1 << PB0) | (1 << PB1) | (1 << PB3) | (1 << PB4);
bool turnout0 = false; bool turnout0 = turnout0Flag;
bool turnout1 = false; bool turnout1 = turnout1Flag;
_delay_ms(100); _delay_ms(100);
setTurnout0(true); setTurnout0(turnout0);
setTurnout1(true); setTurnout1(turnout1);
_delay_ms(500);
setTurnout0(false);
setTurnout1(false);
MCUCR = (1 << ISC00); //enable rising and falling irq on INT0 MCUCR = (1 << ISC00); //enable rising and falling irq on INT0
GIMSK = (1 << INT0); //unmask INT0 GIMSK = (1 << INT0); //unmask INT0